1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to a liquid crystal display device having thin film transistors (TFTs).
2. Discussion of the Related Art
Currently, LCD devices of light weight, thin design, and low power consumption are used in office automation equipment and video units, for example. These LCD devices typically use optical anisotropy of a liquid crystal, wherein thin, long liquid crystal molecules are manipulated for orientation alignment. The alignment direction of the liquid crystal molecules is controlled by application of an electric field to the liquid crystal molecules. When the alignment direction of the liquid crystal molecules are properly adjusted, the liquid crystal is aligned and light is refracted along the alignment direction of the liquid crystal molecules to display image data.
Presently, an active matrix (AM) LCD having a plurality of thin film transistors (TFTs) and pixel electrodes are arranged in shape of an array matrix is proposed because of its high resolution and superiority in displaying moving images. Each of the plurality of TFTs serve to switch a corresponding pixel to transmit incident light. Since amorphous silicon is relatively easy formed on large, inexpensive glass substrates, amorphous silicon thin film transistors (a-Si:H TFTs) are widely used. Alternatively, polysilicon (poly-Si) TFTs having polysilicon active layers have recently been developed to function as switching devices for the LCD devices. Since electron mobility of polysilicon is 100 to 200 times higher than the electron mobility of amorphous silicon, polysilicon TFTs exhibit superior response times. Polysilicon TFTs further exhibit superior stability against temperature and light, and circuits for driving the polysilicon TFTs can be formed on the same substrate where the polysilicon TFTs are formed.
FIGS. 1 and 2 show a conventional array substrate 1 having a polysilicon TFT.
In FIG. 2, a buffer layer 20 made of silicon oxide, for example, is formed on a substrate 10. A TFT active layer 31, a source region 32, a drain region 33, and a storage portion 35 including side portions 35b and 35c, and a capacitor active layer 35a formed of polysilicon, are formed on the buffer layer 20. The source region 32, the drain region 33, and the side portions 35b and 35c of the storage portion 35 are doped with impurities. A gate insulating layer 40 is formed to cover the TFT active layer 31 and the capacitor active layer 35a, and a gate electrode 52 and a capacitor electrode 55 are formed respectively over the TFT active layer 31 and the capacitor active layer 35a. The gate electrode 52 is integrally connected with a gate line 51a. The storage portion 35 and the capacitor electrode 55 comprise a storage capacitor “C.” An interlayer-insulating layer 60 formed of silicon oxide or silicon nitride is formed to cover the gate electrode 52 and the capacitor electrode 55. The interlayer-insulating layer 60 includes a first contact hole 61 and a second contact hole 62 that expose the source region 32 and the drain region 33, respectively.
A data line 71, a source electrode 72, and a drain electrode 73 are formed of a conductive material such as metal, for example, on the interlayer insulating layer 60. The data line 71 perpendicularly crosses gate lines 51a and 51b, thereby defining a pixel region “P.” The source electrode 72 integrally protrudes from the data line 71, and the drain electrode 73 is disposed opposite to the source electrode 71 with the gate electrode 52 centered therebetween. The source and drain electrode 72 and 73 are respectively connected with the source and drain region 32 and 33 via the first and second contact holes 61 and 62.
A passivation layer 80 covers an overall surface of the substrate 10 where the above-described layers are formed. A third contact hole 81 is formed through the passivation layer 80, thereby exposing the drain electrode 73. A pixel electrode 91 is formed on the passivation layer 80 and electrically contacts the drain electrode 73 via the third contact hole 81. In the above-described structure, the capacitor electrode 55 and the storage portion 35 of the storage capacitor “C” are independently formed in the pixel region “P,” and a bias voltage is applied to the capacitor active layer 35a such that the capacitor active layer 35a is always turned on.
FIGS. 3A to 3D, show a fabrication method for the conventional array substrate 1 shown in FIG. 2.
In FIG. 3A, the buffer layer 20 formed of silicon oxide is disposed on the substrate 10. Then, a polysilicon layer 30 is formed on the buffer layer and subsequently patterned. A laser annealing method, a metal induced crystallization (MIC) method, a solid phase crystallization (SPC) method, or a direct deposition method may be applied to form the polysilicon layer 30. In the laser annealing method, the substrate is heated to a temperature of about 250° C. (degrees. C.), and an excimer laser beam is applied to an amorphous silicon layer formed on the substrate. In the MIC method, metal is deposited on an amorphous silicon layer, to function as a crystallization seed. In the SPC method, an amorphous silicon layer is heat-treated at a high temperature for a long time. Generally, in both the MIC and SPC methods, an amorphous silicon layer is deposited and recrystallized to form the polysilicon layer 30. When the amorphous silicon layer is recrystallized to form the polysilicon layer, heat is produced, thereby activating alkali ions, such as K+ and Na+, of the substrate 10. At this point, the buffer layer 20 separates the polysilicon layer 30 from the substrate 10, thereby providing protection from the activated alkali ions of the substrate 10.
In FIG. 3B, an insulating layer made of silicon oxide or silicon nitride and a metal layer are sequentially deposited and patterned to form the gate electrode 52, the capacitor electrode 55, and the gate insulating layer 40 on the polysilicon layer 30. Then, the polysilicon layer 30 is subjected to ion doping such that portions of the polysilicon layer 30, except for portions under the gate electrode 52 and the capacitor electrode 55, are doped. Due to the ion-doping, contact resistance increases between the polysilicon layer 30 and a metal layer forming the source and drain electrodes 72 and 73, which will be formed in a later process.
After the polysilicon layer 30 is doped, it is divided into extrinsic regions 32, 33, 35b, and 35c and intrinsic pure regions 31 and 35a. The extrinsic regions 32 and 33 respectively serve as the source region and the drain region, and the intrinsic region 31 serves as the TFT active layer. For the ion doping, a source gas may include atoms selected from Group III or Group V materials. If a source gas containing atoms of Group V materials is used to form the doped source and drain regions 32 and 33, the source and drain regions 32 and 33 become n-type silicon. If a source gas containing atoms of Group III materials are used, the source and drain regions 32 and 33 become p-type silicon.
In FIG. 3C, silicon oxide or silicon nitride is deposited to cover the surface of the substrate 10 and is subsequently patterned to form the interlayer insulating layer 60 to include the first and second contact holes 61 and 62. The first and second contact holes 61 and 62 expose the source region 32 and the drain region 33, respectively. At this point, the gate electrode 52 and the capacitor electrode 55 are completely covered by the interlayer insulating layer 60, thereby providing electrical insulation from the source and drain electrode 72 and 73, which will be formed in a later process.
In FIG. 3D, metal is deposited and subsequently patterned to form the data line 71, the source electrode 72, and the drain electrode 73. The data line 71 orthogonally crosses the gate lines 51a and 51b (in FIG. 1), and the source and drain electrodes 72 and 73 contact the source and drain regions 32 and 33 via the first and second contact holes 61 and 62, respectively.
Returning to FIG. 2, the passivation layer 80 is formed to cover the surface of the substrate 10 where the source and drain electrodes 72 and 73 are formed. At this point, the passivation layer 80 is patterned such that the third contact hole 81 is formed therethrough to expose a contact portion of the drain electrode 73. Then, a transparent conductive material is deposited on the passivation layer 80 and subsequently patterned, thereby forming the pixel electrode 91. The pixel electrode 91 is disposed in the pixel region “P” defined by the gate lines 51a and 51b and the data line 71, and is electrically connected with the contact portion of the drain electrode 73 via the third contact hole 81.
In the above-described array substrate shown in FIG. 1, although the pixel electrode 91 overlaps the gate line 51b and the data line 71 to increase an aperture ratio, an interval is conventionally interposed between the pixel electrode 91 and the gate line 51a, which are disposed in the same pixel region “P.” The interval between the pixel electrode 91 and the gate line 51 a minimizes any capacitive coupling. Accordingly, if the pixel electrode 91 is spaced apart from the gate line 51a by an interval of 2 to 3 μm (micrometer), any induced parasitic capacitance is decreased, thereby creating a uniform displaying quality and decreasing any associated cross-talk.
However, the interval causes misalignment of some liquid crystal molecules (not shown) that are disposed near the interval. The misalignment of the liquid crystal molecules results in a deterioration of the display quality. Therefore, a black matrix (not shown) is usually used to shield the interval and for preventing light from passing through the interval. However, the black matrix deteriorates the aperture ratio and increases power consumption of the LCD device.